Phase-change memory (PCM) is an emerging memory having non-volatile features and bit access capability. Phase-change memory (PCM) beneficially provides fast read/write speeds, is durable, retains data well, and is scalable. PCM can provide random bit access capability. Therefore, PCM may be referred to as phase-change random access memory (PRAM).
A conventional PRAM cell will now be described with reference to FIG. 1. A PRAM cell typically includes a transistor 112 and a PRAM resistor 110. The emitter of the PRAM resistor 110 is connected in series to bit line 114, the transistor 112 is connected to word line 116, and the collector of the transistor 112 is connected to Vss 120. The PRAM resistor 110 is used as the storage element 118 of the PRAM cell.
FIG. 2 shows a conventional PRAM resistor 110 that can be used as the storage element 118 of the conventional PRAM cell of FIG. 1. A conventional PRAM resistor 110 commonly includes a phase change material (PCM) 232, a heater resistor 234, a top electrode 230, and a bottom electrode 236. An active area 238 is defined by the interface between the PCM 232 and the heater resistor 234.
The PRAM cell uses the characteristic behavior of chalcogenide glass, which can be “switched” between two states, i.e., crystalline and amorphous, by the application of heat. The phase change material (PCM) 232 of the PRAM resistor 110 commonly is formed from a phase change compound of group VI chalcogenic elements S, Se, Te with group IV and V elements. For example, conventional PRAM typically uses a chalcogenide alloy of germanium, antimony and tellurium (GeSbTe) called GST.
The phase of the chalcogenic alloy can be changed by applying different temperatures. For example, the chalcogenide alloy can be heated to a high temperature (over 600° C.), at which point the chalcogenide becomes a liquid. Once cooled, the chalcogenide alloy is frozen into an amorphic glass-like state in which the electrical resistance of the chalcogenide alloy is high. By heating the chalcogenide alloy to a temperature above its crystallization point, but below the melting point, the chalcogenide alloy can be transformed into a crystalline state with a much lower resistance. This phase transition process can be completed in as quickly as five nanoseconds.
For example, as shown in FIG. 3A, the phase of chalcogenic alloy can be set or changed by applying different temperature, such as Tm and Tx, for a predetermined period of time. For example, if the PCM 232 is in the amorphous phase, a lower temperature Tx can be applied to the PCM 232 for a longer period of time to set or change the phase of the PCM 232 to the crystalline phase. If the PCM 232 is in the crystalline phase, a higher temperature, e.g., above its melting point temperature Tm, can be applied to the PCM 232 for a short time to reset or change the PCM 232 to the amorphous phase.
As explained above, the amorphous phase typically has a high resistivity and the crystalline phase typically has a low resistivity. The PRAM cell uses the resistivity difference between the amorphous phase and the poly-crystal phase of chalcogenic alloy to provide a storing mechanism. For example, the amorphic, high resistance state can be defined to represent a binary “0”, and the crystalline, low resistance state can be defined to represent a “1”.
For illustrative purposes, FIG. 3B shows a pair of conventional PRAM cells. The first PRAM cell includes a top electrode 340, a phase change material (PCM) 342, a heater resistor 344, and a bottom electrode 346. A word line 348 is used to select the first PRAM cell. The second PRAM cell includes a top electrode 350, a phase change material (PCM) 352, a heater resistor 354, and a bottom electrode 356. A word line 358 is used to select the second PRAM cell. The first and second PRAM cells can share a common bit line 360.
As exemplarily shown in FIG. 3B, the first cell can be set to the crystalline, low resistance state to represent, for example, a binary “1”. The second cell can be set to the amorphic, high resistance state to represent, for example, a binary “0”. The application of heat by the heater resistor 354 to the PCM 352 sets or changes the phase change material to the amorphic, high resistance state in the active area 362.
With reference again to FIGS. 1-3B, the writing mechanism for the PRAM cell is provided by the self-heating resulting from the current flow (Joule effect) through the phase change material interface (e.g., the active area between the heater resistor and the PCM) of the PRAM resistor 110. The reading mechanism for the PRAM cell is provided by the resistance difference of PRAM resistor 110.
In conventional PRAM cells, the minimum size of the contact window between the phase change material (PCM) and the heater resistor film is limited by conventional design rules. That is, the minimum horizontal contact size of the heater resistor film with the PCM is limited or constrained by the conventional design rule associated with the formation of the heater resistor film (e.g., half pitch lithography resolution). Therefore, since the ability to reduce the size of the active area between the PCM and the heater resistor is limited, the minimum writing current needed to program the conventional PRAM cell is limited. That is, the set current and the reset current of the conventional PRAM cell cannot be reduced beyond a minimum amount based on the size of the contact area between the heater resistor and the PCM. Conventional PRAM cells use a bipolar junction transistor (BIT) device to meet the writing current requirements and to reduce cell size.